Copper alloy for wiring, semiconductor device, method for forming wiring and method for manufacturing semiconductor device

ABSTRACT

A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of the crystal grains. The additional element is preferably at least one element selected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag. This Cu wiring is formed by forming a Cu polycrystalline film, forming an additional element layer on this Cu film, and diffusing this additional element from the additional element layer into the Cu film. This copper alloy for wiring is preferred as metal wiring formed for a semiconductor device.

TECHNICAL FIELD

The present invention relates to a copper alloy for wiring, asemiconductor device using said wiring, a method for forming the wiring,and a method for manufacturing the semiconductor device, and inparticular, to a copper alloy for wiring with an improved wiringreliability, a semiconductor device using wiring formed of said copperalloy, a method for forming the wiring, and a method for manufacturingthe semiconductor device.

BACKGROUND ART

Conventionally, aluminum (Ai) or Al alloy has been widely used for awiring material of semiconductor devices. However, with the progressionin miniaturization and high speed operation of semiconductor devices,copper (Cu) has been used as a wiring material for an improvement intransmission delay of wiring, because copper has a lower resistivity. Inaddition, Cu has a melting point of 1083° C., which is higher than themelting point of Al of 660° C., and is generally considered to be highin electromigration (EM) resistance and also excellent in the aspect ofreliability.

When wiring is formed of Cu, since processing by dry etching of Cu isdifficult, a damascene method has been generally used for forming Cuwiring. The damascene method is a method for forming Cu wiring byforming wiring grooves in an insulating film formed on a semiconductorsubstrate, forming a Cu film so as to fill up the grooves, and polishingthe Cu film until the insulating film is exposed so as to remove anexcessive Cu film on the insulating film excluding that in the wiringgrooves, whereby Cu wiring is provided in a buried manner into wiringgrooves.

In addition, for using Cu as a wiring material, it is necessary toprovide a barrier metal film around Cu in order to prevent Cu fromdiffusing into an insulating film and Cu corrosion. In the following,description will be given of a currently generally used manufacturingmethod of a semiconductor device having Cu wiring while referring to thedrawings.

FIGS. 9( a) through (g) are sectional views showing a conventionalmanufacturing method for a semiconductor device. FIG. 9( a) showslower-layer wiring on which upper-layer wiring is to be formed. Thislower-layer wiring is composed of an insulating film 1 a, a barriermetal film 3 a, Cu 4 a, and a barrier insulating film 8 a. Thislower-layer wiring part is also formed by use of processes similar tothose of the upper-layer wiring.

As shown in FIG. 9( b), an insulating film 1 b is formed on thislower-layer wiring, and then as shown in FIG. 9( c), in the insulatingfilm, wiring grooves and wiring holes are formed by lithography andanisotropic etching. Thereafter, as shown in FIG. 9( d), a barrier metalfilm 3 b, which is a conductive film, is formed on the internal surfacesof the wiring grooves and wiring holes, and as shown in FIG. 9( e), in amanner filling up the wiring grooves and wiring holes, a Cu film 4 b isformed on the insulating film 1 b.

Next, as shown in FIG. 9( f), by CMP (Chemical Mechanical Polishing), anexcessive Cu film 4 b and barrier metal film 3 b excluding the partsburied in the wiring grooves and wiring holes are removed. Then, asshown in FIG. 9( g), a barrier insulating film 8 b, which is anisolator, is formed on the entire surface. In such a manner, a Cu wiringstructure whose lower surface and side surfaces have been covered withthe barrier metal film 3 b, which is a conductor, and whose uppersurface has been covered with the barrier insulating film 8 b, which isan insulator, is formed.

However, in Japanese Published Unexamined Patent Application No.2001-298084, there is a description that when a wiring (wiring groove)width is seven times or more a via (also referred to as a wiring hole ora contact hole) diameter, a disconnection owing to a void (cavity) whichis generated under and inside the via, and the disconnection occurs atthe most accelerated rate at around 150° C.

Similarly, in the following publication, there is a description that,when lower-layer wiring to which vias are connected has a wide width,there is voiding on the surface of lower-layer wiring to be a connectingportion, and the disconnection easily occurs during isothermal storageat 190° C.

“Stress-Induced Voiding Under Vias Connected TO Wide Cu Metal Leads”(Proceeding of IEEE International Reliability Physics Symposium 2002,USA, The Electron Device Society and The Reliability Society of theInstitute of Electrical and Electronics Engineers, Inc, Published onApr. 7, 2002, p 312-321)

Next, description will be given of a method for manufacturing aconventional semiconductor device shown in FIGS. 10( a) through (h).This method is a method for forming copper alloy wiring when an alloysputter target disclosed in Japanese Published Unexamined PatentApplication No. 2000-150522 and the like is used. FIG. 10( a) showslower-layer wiring on which an upper layer is to be formed. Thislower-layer wiring part is also formed by processes similar to those ofthe upper layer shown in the following.

First, as shown in FIG. 10( b), an insulating film 1 b is formed on thislower-layer wiring. Then, as shown in FIG. 10( c), in the insulatingfilm 1 b, wiring grooves and wiring holes are formed by lithography andanisotropic etching. Then, as shown in FIG. 10( d), a barrier metal film3 b, as a conductive film is formed on the entire surface including theinternal surfaces of the wiring grooves and wiring holes. Furthermore,an alloy seed layer 10 b to be electrodes when filling up the wiringgrooves and wiring holes is formed on the barrier metal 3 b by asputtering method using a Cu alloy target. Then, as shown in FIG. 10(e), by a plating method or a CVD method (Chemical Vapor DepositionMethod), a Cu film 4 b is formed on the entire surface so as to fill upthe wiring grooves and wiring holes.

Next, as shown in FIG. 10( f), an additional element in the alloy seedlayer 10 b is diffused into the Cu film 4 b by heat treatment, wherebythe Cu film 4 b is alloyed to form a Cu alloy film 6 c.

Next, as shown in FIG. 10( g), an excessive Cu alloy film 6 c andbarrier metal film 3 b on the surface of the insulating film 1 bexcluding the parts buried in the wiring grooves and wiring holes areremoved by CMP, and as shown in FIG. 10( h), a barrier insulating film 8b, which is an insulator, is formed on the entire surface. In such amanner, a Cu wiring structure whose lower surface and side surfaces havebeen covered with the barrier metal film 3 b, which is a conductor, andwhose upper surface has been covered with the barrier insulating film 8b, which is an insulator, is formed.

In addition, in Japanese Published Unexamined Patent Application No.2000-208517, when using metal wiring of a semiconductor device, atechnique using a CuSn alloy seed layer has been disclosed.

With regard to reliability of Cu wiring formed as shown in FIG. 9( a)through (g), in addition to EM resistance, void formation owing to astress induced migration (SM) has become a crucial problem. A tensilestress caused by a difference in thermal expansion coefficients betweenthe Cu and insulating film to be applied to a Cu wiring portion servesas a driving force of the void formation.

Correspondingly, as described in the above-described Japanese PublishedUnexamined Patent Application No. 2001-298084 and the above-describedpublication, a disconnection owing to a void formation occurs. Such afailure caused by stress is expected to become more prominent when thevia diameter is further reduced by miniaturization of the element.

In addition, as countermeasures against EM and SM, priorly, alloying ofCu wiring has been investigated in numerous cases. In alloying, bychanging Cu composition, migration resistance of Cu can be improved.

However, as in the above-described Japanese Published Unexamined PatentApplication No. 2000-208517, Cu alloy wiring formed by the method shownin FIG. 10( a) through (h) has the following problems. Namely, when analloy seed layer 10 b was formed, by diffusing an additional element inthe alloy seed layer 10 b into the Cu film 4 b by heat treatment, a Cualloy is formed. On the other hand, the additional element in the alloyseed layer 10 b is diffused into the Cu film 4 b by heat treatment, andis partly precipitated on crystal grain boundaries 7 b of the Cu alloyfilm 6 c, however, the additional element mostly remains in crystalgrains of the Cu alloy film 6 c. Electron scattering occurs under theinfluence of this additional element remaining in crystal grains of theCu alloy film 6 c.

In addition, under the influence of grain boundary scattering ofelectrons as a result of a reduction in the size of Cu crystal grains byheat treatment, resistivity of the formed Cu alloy wiring rises.

Furthermore, although it is ideal that the additional element in thealloy seed layer 10 b uniformly diffuses into the Cu film 4 b, if thediffusion speed of the additional element into the Cu film 4 b is slow,the additional element remains in the alloy seed layer 10 b in largequantity. At this time, under the influence of the additional elementremaining in the alloy seed layer 10 b in large quantity, resistivity ofthe Cu wiring rises, and also concentration profiles of the additionalelement in the bulk Cu film 6 c can change as a result of heat treatmentto form wiring of a more upper layer, therefore, instability occurs withrespect to a heat cycle at the time of multi-layer formation.

Furthermore, under the influence of the additional element in the alloyseed layer 10 b, growth of the crystal grains of the Cu film 6 c issuppressed. Particularly, in such a case where the additional element isprecipitated on Cu crystal grain boundaries, pinning of the grainboundaries occurs under the influence of the precipitated additionalelement, and growth of the Cu crystal grains in heat treatment issuppressed. As a result, since the diameter of Cu crystal grains isreduced, this raises resistivity of the Cu wiring and also exerts aninfluence on a decline in wiring reliability caused by EM and SM and thelike.

In addition, when the Cu alloy seed layer 10 b is formed by sputtering,since Cu filling capability by sputtering is different depending on thewidth of the wiring groove and wiring hole, inconvenience occurs.Namely, with narrow wiring, since sputter filling capability isdeteriorated, the alloy seed layer 10 b deposited on the bottom of thewiring groove has a thin film thickness. Therefore, concentration of theadditional element in the Cu wire in a narrow-width wiring groovebecomes relatively small compared to that of a wide-width wiring groove.As a result, the Cu wires in the narrow-width wiring groove has a lowresistivity compared to that of a wide-width wiring groove. As such,when the alloy seed layer 10 b is formed by a sputtering method, sinceconcentration of the additional element is different depending on thewidth of the wiring groove, resistivity of the Cu wiring variesdepending on the width of the wiring groove.

Furthermore, in the above-described Japanese Published Unexamined PatentApplication 2000-208517, it has been reported that adhesion between thebarrier metal film and the alloy seed layer is deteriorated when a CuSnalloy seed layer is used. As such, securing adhesion between the barriermetal layer 3 b and alloy seed layer 10 has also become a crucialproblem.

An object of the present invention is to provide a highly reliablecopper alloy for wiring for which wiring delay has been improved, whichis high in performance, and which is excellent in SM resistance and EMresistance, a semiconductor device using the same wiring, a method forforming the wiring, and a method for manufacturing the semiconductordevice.

DISCLOSURE OF THE INVENTION

A copper alloy for wiring according to the present invention is composedof a polycrystalline copper alloy consisting of Cu (copper) as aprimarily element and an or a primarily of additional element(s),wherein the concentration of said additional element is, at grainboundaries of crystal grains of said polycrystalline copper alloy and invicinities of grain boundaries, higher than that of the inside of thecrystal grains.

According to this invention, by introducing an additional element intoCu crystal grain boundaries and vicinities of crystal grains which serveas diffusion paths of SM or EM in wiring at a high concentration, Cumigration along the Cu crystal grain boundaries can be suppressed,whereby reliability of a metal for wiring can be improved. Furthermore,by this invention, a metal for wiring for which wiring delay has beensuppressed and which is high in performance can be provided.

In this copper alloy for wiring, it is preferable that the additionalelement is at least one element selected from a group consisting of Ti(titanium), Zr (zirconium), Hf (hafnium), Cr (chromium), Co (cobalt), Al(aluminum), Sn (tin), Ni (nickel), Mg (magnesium), and Ag (silver).

The additional element is an element whose solid solubility limit in aCu film is 1 atomic percent or less and whose diffusion coefficient atCu crystal grain boundaries is great, and by adding this additionalelement to the inside of the Cu film, the additional element can beintroduced into crystal grain boundaries of the Cu film and vicinitiesof crystal grain boundaries at a high concentration. Therefore, Cumigration along the Cu crystal grain boundaries can be suppressed,whereby reliability of wiring can be improved.

In the copper alloy for wiring of the present invention, for example, atthe crystal grain boundaries and/or in the vicinities of grainboundaries, intermetallic compounds of Cu with at least one elementselected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg,and Ag are formed.

According to this invention, by forming stable intermetallic compoundsat Cu crystal grain boundaries and in vicinities of crystal grainboundaries (frontmost surfaces of Cu crystal grains) which serve asdiffusion paths of SM or EM, Cu migration along the Cu crystal grainboundaries can be suppressed, whereby reliability of wiring can beimproved.

In addition, in the copper alloy for wiring of the present invention,for example, at the crystal grain boundaries and/or in the vicinities ofgrain boundaries, oxides of at least one element selected from a groupconsisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag are formed.

According to this invention, by forming stable metal oxides at Cucrystal grain boundaries and in vicinities of crystal grain boundaries(frontmost surfaces of Cu crystal grains) which serve as diffusion pathsof SM or EM, Cu migration along the Cu crystal grain boundaries can besuppressed, whereby reliability of wiring can be improved.

In the copper alloy for wiring of the present invention, it ispreferable that concentration of the additional element of the inside ofthe crystal grains is 0.1 atomic percent or less.

According to this invention, by providing a construction wherein anadditional element is introduced into Cu crystal grain boundaries andvicinities of crystal grain boundaries which serve as diffusion paths ofSM or EM at a high concentration, while inside the crystal grains, anextremely slight amount of the additional element of 0.1 atomic percentor less is contained, Cu migration along Cu crystal grain boundaries canbe suppressed, whereby reliability of wiring can be improved.

A semiconductor device according to the present invention ischaracterized in that, on a substrate on which a semiconductor elementhas been formed, metal wiring composed of the copper alloy for wiring asset forth in any one of Claims 1 through 5 of the present application isformed.

According to this invention, by introducing an additional element intoCu crystal grain boundaries and vicinities of crystal grain boundarieswhich serve as diffusion paths of SM or EM in metal wiring of asemiconductor device at a high concentration, Cu migration along Cucrystal grain boundaries can be suppressed, whereby reliability of metalwiring can be improved. Furthermore, by this invention, a semiconductordevice having metal wiring for which wiring delay has been suppressedand which is high in performance can be provided.

A forming method for wiring according to the present invention comprisesthe steps of: forming a polycrystalline Cu film; forming a layer formedof an additional element which is to be added into the Cu film on thepolycrystalline Cu film; and diffusing the additional element from theadditional element layer into the polycrystalline Cu film.

According to this invention, since crystal grains of a Cu film are grownin a polycrystalline Cu film forming step and an additional element isintroduced into this polycrystalline Cu film, no such suppression of Cucrystal grain growth owing to an influence of an additional element inheat treatment as observed in a case where a Cu alloy seed layer isformed by use of a sputter target in which an additional element hasbeen mixed at a few percent occurs. In addition, since the additionalelement hardly exists inside bulk crystal grains, electron scattering inthe bulk crystal grains by the additional element is suppressed, andresistance of the copper alloy for wiring can be lowered. As a result,highly reliable wiring for which wiring delay has been suppressed, whichis high in performance, and which is excellent in SM resistance and EMresistance can be obtained.

In the forming method for wiring, a heating step of heating a substrateon which the polycrystalline Cu film has been formed, a step of formingthe additional element layer, and a step of diffusing the additionalelement can be simultaneously performed.

According to this invention, in addition to the effects as mentionedabove, by simultaneously performing these respective steps, the wiringforming steps can be simplified by omitting several steps.

The additional element is at least one element selected from a groupconsisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag.

Since these additional elements are elements whose solid solubilitylimits are 1 atomic percent or less and whose diffusion coefficients atCu crystal grain boundaries are great, an additional element can beintroduced into Cu crystal grain boundaries and vicinities of crystalgrain boundaries at a high concentration. Therefore, Cu migration alongCu crystal grain boundaries can be suppressed, whereby reliability ofwiring can be improved.

A method for manufacturing a semiconductor device according to thepresent invention comprises the steps of: forming a polycrystalline Cufilm on a substrate on which a semiconductor element has been formed;forming a layer composed of an additional element on the polycrystallineCu film; and diffusing the additional element from the additionalelement layer into the polycrystalline Cu film.

According to this invention, since Cu crystal grains are grown in apolycrystalline Cu film forming step and an additional element isintroduced into this polycrystalline Cu film, no such suppression of Cucrystal grain growth owing to an influence of an additional element inheat treatment as observed in a case where a Cu alloy seed layer isformed by use of a sputter target in which an additional element hasbeen mixed at a few percent occurs. In addition, since the additionalelement hardly exists inside bulk Cu crystal grains, electron scatteringin the bulk crystal grains by the additional element is suppressed, andresistance of the Cu wiring in a semiconductor device can be lowered. Asa result, a highly reliable metal wiring in which wiring delay has beensuppressed, which is high in performance, and which is excellent in SMresistance and EM resistance can be obtained.

Another method for manufacturing a semiconductor device according to thepresent invention comprises the steps of: forming an insulating film ona substrate on which a semiconductor element has been formed; formingconcavities for wiring composed of at least either grooves or holes inthe insulating film; forming a Cu film on the insulating film so as tofill up the concavities for wiring; removing an excessive Cu film on theinsulating film excluding parts buried in the concavities for wiring bychemical mechanical polishing; forming a layer composed of an additionalelement on the Cu film; diffusing the additional element from theadditional element layer into the Cu film; and removing an excessiveadditional element layer.

According to this invention, Cu crystal grains are grown in apolycrystalline Cu film forming step, and an additional element isintroduced into this polycrystalline Cu film. Therefore, no suchsuppression of Cu crystal grain growth owing to an influence of anadditional element by heat treatment as observed in a case where a Cualloy seed layer is formed by use of a sputter target in which anadditional element has been mixed at a few percent occurs. In addition,since the additional element hardly exists inside bulk Cu crystalgrains, electron scattering in the bulk Cu crystal grains by theadditional element is suppressed, and resistance of the Cu wiring in asemiconductor device can be lowered. Furthermore, according to thepresent invention, since an additional element is introduced (diffusedinto Cu) into a Cu film from an additional element layer of an upperlayer after a Cu film is buried in the concavities for wiring, such adifference in concentration of the additional element owing to adifference in Cu filling capability between respective grooves andrespective holes hardly occurs, said difference has been observed in acase where a Cu alloy seed layer is formed by use of a sputter target,and the wiring grooves and wiring holes are filled with Cu. As a result,unevenness in resistivity of Cu wiring depending on the width of wiringgrooves is eliminated.

Still another method for manufacturing a semiconductor device accordingto the present invention comprises the steps of: forming an insulatingfilm on a substrate on which a semiconductor element has been formed;forming concavities for wiring composed of at least either grooves orholes in the insulating film; forming a barrier metal to prevent Cu fromdiffusing on the insulating film including inner surfaces of theconcavities for wiring; forming a Cu film on the insulating film so asto fill up the same in the concavities for wiring; removing a Cu filmand a barrier metal film excluding parts buried in the concavities forwiring by chemical mechanical polishing; forming a layer composed of anadditional element on the Cu film in the concavities for wiring;diffusing the additional element from the additional element layer intothe Cu film; and removing an excessive additional element layer.

According to this invention, since Cu crystal grains are grown in apolycrystalline Cu film forming step, and an additional element isintroduced into this polycrystalline Cu film, no suppression of Cucrystal grain growth owing to an influence of an additional element inheat treatment occurs. In addition, since the additional element hardlyexists inside bulk Cu crystal grains, electron scattering in the bulk Cucrystal grains by the additional element is suppressed, and resistanceof the Cu wiring in a semiconductor device can be lowered. In addition,since an additional element is introduced into a Cu film from anadditional element layer of an upper layer after a Cu film is buried, adifference in concentration of the additional element in Cu wiringbecomes unlikely to occur, thus unevenness in resistivity of Cu wiringdepending on the width of wiring grooves is eliminated. Furthermore,since a barrier metal is provided between the Cu and insulating film,diffusion of Cu into the insulating film and corrosion of Cu can beprevented.

In the present invention, before a step of removing the excessive Cufilm, a step of forming the additional element layer, a step ofdiffusing the additional element, and a step of removing the excessiveadditional element layer can be performed.

According to this invention, as a result of a formation of stableintermetallic compounds of Cu and an additional element at Cu crystalgrain boundaries and in vicinities of crystal grain boundaries, EMresistance and SM resistance are improved, whereby reliability of wiringof an semiconductor device is improved.

In addition, in the present invention, after a step of removing theexcessive Cu film, a step of forming the additional element layer, astep of diffusing the additional element, and a step of removing theexcessive additional element layer can be performed.

According to the present invention, by performing a step of forming theadditional element layer, a step of diffusing the additional element,and a step of removing the excessive additional element layer after astep of removing the excessive Cu film, stable intermetallic compoundsof Cu and an additional element are formed on the surfaces of Cu crystalgrains which are in contact with a layer formed on the Cu film, which isa metal for wiring. As a result, adhesion between the Cu of a metal forwiring and upper layer is improved, whereby reliability of wiring of ansemiconductor device is improved.

In the method for manufacturing a semiconductor device of the presentinvention, a step of heating the substrate, a step of forming theadditional element layer, and a step of diffusing the additional elementcan be simultaneously performed.

According to this invention, in addition to the effects as mentionedabove, by simultaneously performing these respective steps,manufacturing of a semiconductor device can be simplified by omittingthe severed steps.

The additional element is at least one element selected from a groupconsisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag.

According to this invention, since the additional element is an elementwhose solid solubility limit in Cu is 1 atomic percent or less and whosediffusion coefficient at Cu crystal grain boundaries is large, by addingthis additional element to a Cu film, the additional element can beintroduced into Cu crystal grain boundaries and vicinities of crystalgrain boundaries at a high concentration. Therefore, Cu migration alongCu crystal grain boundaries can be suppressed, whereby reliability ofmetal wiring of a semiconductor device can be improved.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a sectional view showing a semiconductor device according to afirst embodiment of the present invention.

FIGS. 2( a) through (j) are sectional views showing a method formanufacturing a semiconductor device according to the first embodimentof the present invention in the order of steps.

FIG. 3 is a sectional view showing a semiconductor device according to asecond embodiment of the present invention.

FIGS. 4( a) through (j) are sectional views showing a method formanufacturing a semiconductor device according to the second embodimentof the present invention in the order of steps.

FIG. 5 is a sectional view of a semiconductor device according to athird embodiment of the present invention.

FIGS. 6( a) through (i) are sectional views showing a method formanufacturing a semiconductor device according to the third embodimentof the present invention in the order of steps.

FIGS. 7( a) through (k) are sectional views showing former steps in anexample of the present invention in the order of steps.

FIGS. 8( l) through (s) are similarly sectional views showing lattersteps in an example of the present invention in the order of steps.

FIGS. 9( a) through (g) are sectional views explaining a method formanufacturing a semiconductor device according to the prior art.

FIGS. 10( a) through (h) are sectional views explaining another exampleof a method for manufacturing a semiconductor device according to theprior art.

FIG. 11 is a graph explaining a relationship between the storage timeand relative failure rate of via chains fabricated by an example and acomparative example.

FIG. 12 is a graph showing electromigration resistance of contact holesof via chains fabricated by an example and a comparative example by arelationship between the cumulative time and cumulative failureprobability.

FIG. 13 is a graph showing changes in resistivity of Cu wiring owing toa difference in heat treatment after a Cu layer formation in blanketwafer samples of an example.

FIG. 14 is a graph showing distributions of Ti, Cu, and N of a barriermetal film, a Cu layer, and an additional element layer in blanket wafersamples of an example.

FIG. 15 is a graph showing changes in resistivity of Cu wiring owing toa difference in additional elements and a difference in heat treatmentafter an additional element layer formation in blanket wafer samples ofan example.

FIG. 16 is a graph diagram showing results of a measurement of oxygen(O) distributions in Cu.

FIGS. 17( a) and (b) show scanning electron micrographs in samples shownin FIG. 16.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments of the present invention will be described in detailwith reference to the drawings.

First Embodiment

A Cu wiring structure of a semiconductor device according to a firstembodiment of the present invention will be described with reference toFIG. 1.

A Cu wiring structure of a semiconductor device shown in FIG. 1 has alower-layer wiring composed of an insulating film 1 a, a barrier metalfilm 3 a, Cu 4 a, and a barrier insulating film 8 a, and an upper-layerwiring composed of an insulating film 1 b, a barrier metal film 3 b, Cucrystal grains 6 b, Cu grain boundaries and vicinities thereof 7 b, anda barrier insulating film 8 b. Here, the Cu 4 a of the lower-layerwiring is constructed similarly to the Cu crystal grains 6 b and Cugrain boundaries and vicinities thereof 7 b of the upper wiring.

And, the feature of the first embodiment is a structure wherein at leastany of a large quantity of an additional element, intermetalliccompounds of Cu and an additional element, and oxides of an additionalelement have been precipitated on boundaries of Cu crystal grains 6 band vicinities thereof and interfaces between the Cu grain grains 6 band the barrier metal film 3 b and vicinities thereof (shown asreference numeral 7 b).

Cu metal wiring is made of a Cu polycrystal doped with a metallicelement other than Cu. The Cu crystal grains 6 b composing thepolycrystal are Cu crystal grains whose crystal grain growth is notrestricted and which has an average and appropriate size on the order of1 μm to 10 μm.

And, the Cu crystal grain boundaries 7 b and the interfaces 7 b betweenthe Cu crystal grains 6 b and the barrier metal layer 3 b have astructure wherein the additional element or compounds containing theadditional element (intermetallic compounds with Cu, oxides or the like)have been precipitated. In addition, there is a structure wherein,intermetallic compounds of the additional element with Cu or the likehave been formed, in addition to the Cu crystal grain boundaries and thelike, in the vicinities 7 b of Cu crystal grains. Here, the vicinitiesCu crystal grain boundaries herein mentioned indicate positions on theorder of 10 nm inward from the crystal grain surfaces of the Cu crystalgrains 6 b.

Although concentration of the additional element at the grain boundariesof the Cu crystal grains 6 b and vicinities 7 b of grain boundaries isnot particularly limited, an additional element of a larger quantitythan that of at least the inside of the Cu crystal grains 6 b exists atthe grain boundaries of the Cu crystal grains 6 b and vicinities 7 b ofgrain boundaries. Concretely, concentration of the additional element atthe grain boundaries of the Cu crystal grains 6 b and vicinities 7 b ofgrain boundaries is on the order of 2 to 1000 times the additionalelement concentration at the inside of the Cu crystal grains 6 b, andpreferably, on the order of 10 to 100 times.

It is possible to measure additional element concentration at the Cucrystal grain boundaries and vicinities thereof 7 b by, for example,X-ray spectroscopy. This measuring method is detectable when theadditional element concentration at Cu crystal grains and vicinitiesthereof 7 b is 0.1 atomic percent (hereinafter, atomic percent isreferred to as atomic %) or more.

On the other hand, inside the Cu crystal grains 6 b, in other words, inbulk Cu 6 b, only an additional element of 0.1 atomic % or less exists,which is a nearly pure Cu condition. Here, the inside of the Cu crystalgrains herein mentioned means a part of Cu crystal grains excluding theaforementioned vicinities of Cu crystal grain boundaries.

It is possible to measure additional element concentration at the insideof the Cu crystal grains 6 b by, for example, SIMS (Secondary Ion MassSpectroscopy), X-ray spectroscopy or the like. SIMS can be used whenmeasuring Cu crystal grains have a diameter greater than a beam diameter(normally, a few tens of micrometers) used in SIMS. When the Cu crystalgrain diameter is smaller than the same, by determining an averageconcentration of the additional element at an area including grainboundaries and the inside of the Cu crystal grains by SIMS and bydetermining an additional element concentration at the aforementioned Cucrystal grain boundaries and vicinities 7 b of grain boundaries, anadditional element concentration at the inside of the Cu crystal grainscan be estimated. In addition, by X-ray spectroscopy from the Cu crystalsurface, additional element concentration can be measured if the atomicpercent is 1 or more. Here, detection sensitivity by X-ray spectroscopyis on the order of 0.1 atomic percent.

As such, at positions of the grain boundaries of Cu crystal grains andvicinities 7 b of grain boundaries, concentration (content) of theadditional element is provided higher than that of the inside of the Cucrystal grains 6 b.

In addition, as the additional element, an element whose solidsolubility limit in Cu is 1 atomic % or less and whose diffusioncoefficient at Cu crystal grain boundaries is great can be used. Adiffusion coefficient of the additional element at Cu bulk (inside ofthe Cu crystal grains) does not necessarily have to be great. As theadditional element, in particular, titanium (Ti), zirconium (Zr),hafnium (Hf), chromium (Cr), and cobalt (Co) are preferably used. As theadditional element, in addition, aluminum (Al), tin (Sn), nickel (Ni),magnesium (Mg), and silver (Ag) can be used.

In such a Cu wiring structure, no such problem in the prior art thatresistivity of Cu wiring is increased under the influence of electronscattering owing to the additional element remaining in the bulk Cu 6 cand under the influence of boundary scattering of electrons owing to areduction in size of crystal grains occurs. In addition, by such astructure of Cu metal wiring, electron scattering owing to theadditional element in the bulk Cu 6 b can be suppressed, wherebytransmission delay of wiring can be improved. In addition, on Cu crystalgrain boundaries and vicinities 7 b of the crystal grain boundarieswhich serve as diffusion paths of Cu for void formation, the additionalelement or compounds including the additional element are precipitated,whereby Cu diffusion is suppressed.

Furthermore, when an element which is higher in reducibility than Cu andis easily oxidized is used as an additional element, even if the Cumetal wiring is exposed to oxygen or vapor, the additional element whichis present on the boundaries is first oxidized, and the oxidizedadditional element functions as a barrier to prevent Cu oxidation,therefore, provided is an effect of a Cu oxidation prevention anderosion prevention. In addition, by forming a layer of an element whichis higher in reducibility than Cu and is easily oxidized on the Cusurface, provided are an effect to suppress Cu from oxidizing in heattreatment and a gettering effect for oxygen and impurities which arepresent on the Cu surface and inside Cu. The oxygen which is present onthe Cu surface and in Cu can diffuse during heat treatment and oxidize abarrier film of a lower layer, and in this case, adhesion between the Cuand barrier metal is deteriorated, which exerts a harmful effect onreliability of wiring. Gettering of oxygen which is present on the Cusurface and in Cu also leads to suppressing barrier metal fromoxidizing, which is effective for an improvement in reliability of Cuwiring.

Herein, as Cu migration paths which causes the problem of reliability ofCu wiring, it has been indicated in a publication ((Electromigrationpath in Cu thin-film lines), (Applied Physics Letters, USA, AmericanInstitute of Physics, published on May 17, 1999), Vol. 74, p 2945-2947)and the like that, as regards EM, diffusion at interfaces between the Cucrystal grains and the barrier insulating films or between the Cucrystal grain boundaries is more dominant than diffusion in bulk Cu.

In addition, as regards to SM, as well, since voids owing to SM areformed at crystal grain boundaries, it is considered that the Cu crystalgrain boundaries serve as diffusion paths. Therefore, it is consideredimportant for an improvement in reliability of Cu metal wiring tosuppress interfacial and grain boundary diffusion. Accordingly, it isconsidered that Cu metal wiring is improved in reliability by alloyingbecause, as a result of precipitation of an added impurity element atinterfaces between the Cu crystal grains and the other layers or betweenthe Cu crystal grain boundaries, Cu diffusion via the interfaces betweenthe Cu crystal grains and the other layers and between the Cu crystalgrain boundaries is suppressed.

In the present invention, by suppressing alloying of bulk Cu andintroducing the additional element into only the interfaces between theCu crystal grains and the other layers and between the Cu crystal grainboundaries, a rise in resistance of Cu wiring is suppressed, thusprovision of highly reliable Cu metal wiring with EM and SM resistanceis realized.

Next, a method for manufacturing a semiconductor device having Cu wiringof the first embodiment will be described with reference to FIGS. 2( a)through (j).

FIG. 2( a) shows lower-layer wiring on which upper-layer wiring is to beformed. This lower-layer wiring is composed of an insulating film 1 a, abarrier metal film 3 a, Cu 4 a, and a barrier insulating film 8 a. Thislower-layer wiring part is also formed by use of processes similar tothose of the upper-layer wiring shown in the following.

As shown in FIG. 2( b), an insulating film 1 b is formed on thislower-layer wiring, and then as shown in FIG. 2( c), in the insulatingfilm 1 b, wiring grooves and wiring holes are formed by lithography andanisotropic etching. Thereafter, as shown in FIG. 2( d), a barrier metalfilm 3 b is formed on the formed wiring grooves and wiring holes, and Cu4 b is buried therein. Next, and as shown in FIG. 2( e), heat treatmentfor grain growth of Cu is applied. This heat treatment is performed at alow temperature of not more than 400° C., and, preferably, not more than300° C. It is also possible to omit this heat treatment for Cu graingrowth.

Thereafter, as shown in FIG. 2( f), a layer 5 b of an element to beadded to the inside of Cu crystals is formed on the surface of the Cu 4b. Next, as shown in FIG. 2( g), heat treatment to diffuse theadditional element 5 b into the Cu crystals 4 b is applied. Thetemperature of this heat treatment is set to 300° C. to 500° C., and thetime is set to ten minutes to 1 hour.

Next, as shown in FIG. 2( h), an excessive additional element layer 5 bis removed by wet etching. For a removal of the additional element layer5 b, CMP may be used in place of wet etching. Subsequently, as shown inFIG. 2( i), an excessive Cu 6 b and barrier metal layer 3 b excludingthe wiring grooves and wiring holes are removed by CMP. Next, as shownin FIG. 2( j), a barrier insulating film 8 b to prevent Cu fromcorroding and diffusing is formed on the entire front surface.

By repeating the steps of FIG. 2( b) to FIG. 2( j), wiring of a moreupper layer can be formed.

In the above manufacturing method, although formation of the additionalelement layer 5 b (FIG. 2( f)) and diffusion of the additional elementinto the Cu polycrystal (FIG. 2( g)) have been separately performed, itis also possible to simultaneously perform formation of the additionalelement layer 5 b and diffusion of the additional element into the Cupolycrystal by forming the additional element layer 5 b at a hightemperature. By simultaneously performing these two steps, the number ofsteps can be reduced, thus a semiconductor device having Cu wiring canbe more simply manufactured. Here, temperature and time when the twosteps are simultaneously performed as such may be provided similarly tothose of heat treatment to diffuse the additional element into Cucrystals. The same applies to respective embodiments to be described inthe following.

In addition, although, in the present embodiment, Cu has been buriedafter the barrier metal film 3 b was formed, the barrier metal film 3 bis not an essential construction and may not be formed. Here, by formingthe barrier metal film 3 b, diffusion of the Cu 6 b into the insulatingfilm 1 b can be suppressed.

In addition, although, in the above, a description has been given by useof a dual damascene method for simultaneously forming wiring grooves andwiring holes, the invention is also similarly applied to a wiring layerformation when a single damascene method for forming only wiring groovesor only wiring holes is used. Here, in the present invention, the wiringgrooves and wiring holes are also collectively referred to asconcavities for wiring.

Second Embodiment

A Cu wiring structure of a semiconductor device according to a secondembodiment of the present invention will be described with reference toFIG. 3.

In the Cu wiring structure shown in FIG. 3, in addition to theconstruction of the first embodiment, a stable intermetallic compoundlayer of Cu with an additional element is formed at interfaces betweenthe barrier insulating film 8 b and Cu crystal grains 6 b. Thereby,adhesion between the Cu 6 b, which is a metal for wiring, and barrierinsulating film 8 b is improved, thus reliability of wiring is improved.

Next, a method for manufacturing a semiconductor device having Cu wiringof the second embodiment will be described with reference to FIG. 4( a)through (j).

Although the manufacturing method of the second embodiment is differentfrom that of the first embodiment in a point that an additional elementlayer 5 b is formed after an excessive Cu 6 b and an excessive barriermetal 3 b are removed by CMP, others are the same.

FIG. 4( a) shows lower-layer wiring on which upper-layer wiring is to beformed. This lower-layer wiring part is also formed by use of processessimilar to those of the upper-layer wiring shown in the following.

As shown in FIG. 4( b), an insulating film 1 b is formed on thislower-layer wiring, and then as shown in FIG. 4( c), in the insulatingfilm 1 b, wiring grooves and wiring holes are formed by lithography andanisotropic etching. Thereafter, as shown in FIG. 4( d), a barrier metalfilm 3 b is formed, and Cu 4 b is buried. Next, and as shown in FIG. 4(e), heat treatment for grain growth of the buried Cu is applied. Thisheat treatment is performed at a low temperature of not more than 400°C., and, preferably, not more than 300° C. It is also possible to omitthis heat treatment for Cu grain growth.

Thereafter, as shown in FIG. 4( f), excessive Cu and an excessivebarrier metal excluding the wiring grooves and wiring holes are removedby CMP. Next, as shown in FIG. 4( g), a layer 5 b of an element to beadded into the Cu is formed on the Cu surface. Next, as shown in FIG. 4(h), heat treatment to diffuse the additional element into the Cu isapplied. The temperature of this heat treatment is set on the order of300° C. to 500° C., and the time is set on the order of 10 minutes to 1hour.

Next, as shown in FIG. 4( i), an excessive additional element layer 5 bis removed by wet etching. For a removal of the additional element layer5 b, CMP may be used in place of wet etching. Next, as shown in FIG. 4(j), a barrier insulating film 8 b to prevent Cu from corroding anddiffusing is formed on the entire front surface.

By repeating FIG. 4( b) to FIG. 4( j), wiring of a more upper layer canbe formed.

In the above manufacturing method, although formation of the additionalelement layer 5 b (FIG. 4( g)) and diffusion of the additional elementinto the Cu polycrystal (FIG. 4( h)) have been separately performed, itis also possible to simultaneously perform formation of the additionalelement layer 5 b and diffusion of the additional element into the Cupolycrystal by forming the additional element layer 5 b under ahigh-temperature condition. By simultaneously performing these twosteps, the number of steps can be reduced, thus a semiconductor devicehaving Cu wiring can be more simply manufactured.

In addition, although, a description has been given in the above by useof a dual damascene method for simultaneously forming wiring grooves andwiring holes, the invention is also similarly applied to a formation ofconcavities for wiring when a single damascene method for forming onlywiring grooves or only wiring holes is used.

Third Embodiment

A Cu wiring structure of a semiconductor device according to a thirdembodiment of the present invention will be described with reference toFIG. 5.

The wiring structure of the third embodiment shown in FIG. 5 isdifferent from the structure of the second embodiment in a point that nobarrier insulating film 8 b is used. In the third embodiment, since, byforming a stable intermetallic compound layer on the Cu surface,oxidation and corrosion of the Cu are prevented, the barrier insulatingfilm 8 b becomes unnecessary. Since an effective dielectric constant ofCu wiring is lowered by providing no barrier insulating film 8 b,transmission delay can be improved.

Next, a method for manufacturing a semiconductor device having Cu wiringof the third embodiment will be described with reference to FIG. 6( a)through (i).

FIG. 6( a) shows a lower-layer wiring on which an upper-layer wiring isto be formed. This lower-layer wiring part is also formed by use ofprocesses similar to those of the upper-layer wiring shown in thefollowing.

As shown in FIG. 6( b), an insulating film 1 b is formed on thislower-layer wiring, and then as shown in FIG. 6( c), in the insulatingfilm 1 b, wiring grooves and wiring holes are formed by lithography andanisotropic etching. Thereafter, as shown in FIG. 6( d), a barrier metalfilm 3 b is formed, and Cu 4 b is buried. Next, and as shown in FIG. 6(e), heat treatment for growth of Cu crystal grains is applied. This heattreatment is performed at a low temperature of not more than 400° C.,and, preferably, not more than 300° C. It is also possible to omit thisheat treatment for Cu grain growth.

Thereafter, as shown in FIG. 6( f), an excessive Cu and barrier metalexcluding the wiring grooves and wiring holes are removed by CMP. Next,as shown in FIG. 6( g), a layer 5 b of an element to be added to theinside of Cu is formed on the Cu surface. Next, as shown in FIG. 6( h),heat treatment to diffuse the additional element into Cu is applied. Thetemperature of this heat treatment is set to 300° C. to 500° C., and thetime is set to 10 minutes to 1 hour.

Next, as shown in FIG. 6( i), an excessive additional element layer 5 bis removed by wet etching. For a removal of the additional element layer5 b, CMP may be used in place of wet etching.

By repeating FIG. 6( b) to FIG. 6( i), wiring of a more upper layer canbe formed.

In the above manufacturing method, although formation of the additionalelement layer 5 b (FIG. 6( g)) and diffusion of the additional elementinto the Cu polycrystal (FIG. 6( h)) have been separately performed, itis also possible to simultaneously perform formation of the additionalelement layer 5 b and diffusion of the additional element into the Cupolycrystal by forming the additional element layer 5 b at a hightemperature. By simultaneously performing these two steps, the number ofsteps can be reduced, thus a semiconductor device having Cu wiring canbe more simply manufactured.

In addition, although, a description has been given in the above by useof a dual damascene method for simultaneously forming wiring grooves andwiring holes, the invention is also similarly applied to a formation ofconcavities for wiring when a single damascene method for forming onlywiring grooves or only wiring holes is used.

Hereinafter, characteristics of an example and a comparative example ofthe present invention are compared, and effects of the present inventionwill be described.

EXAMPLE

FIGS. 7( a) through (k) and FIGS. 8( l) through (s) are sectional viewsshowing a method for manufacturing a semiconductor device in an exampleof the present invention in the order of steps.

A 1000 nm SiO₂ film (insulating film) 1 a was formed on a siliconsubstrate (unillustrated), thereon a first wiring layer (wiring grooves)was formed by a single damascene method, and then, on the top thereof,by a dual damascene method, a second wiring layer (wiring grooves) andcontact holes (wiring holes) with the first wiring layer were formed.The details will be described in the following.

On the SiO₂ film 1 a (FIG. 7( a)), a SiC film (stopper insulating film)2 a with a thickness of 50 nm to be an etching stopper was formed, andsubsequently, as shown in FIG. 7( b), a SiO₂ film (insulating film) 1 bwith a thickness of 350 nm to insulate wirings each other in the firstwiring layer was formed, and as shown in FIG. 7( c), wiring grooves wereformed, by lithography and etching, in the SiO₂ film 1 b. Thereafter, asshown in FIG. 7( d), a barrier metal film 3 a composed of a TaN film anda Ta film and a 100 nm Cu thin film were formed on the entire surface ofa substrate surface, and while using this Cu film as an electrode, Cu 4a was buried by an ionization sputtering method.

Next, as shown in FIG. 7( e), after applying heat treatment in anitrogen atmosphere for Cu crystal grain growth, as shown in FIG. 7( f),a Ti film (additional element layer) 5 a with a film thickness of 20 nmwas formed on the entire Cu front surface by sputtering.

Subsequently, as shown in FIG. 7( g), a heat treatment at 350° C. for 30minutes was performed in a nitrogen atmosphere, whereby Ti was diffusedinto Cu from the Cu surface. Here, since Ti is diffused via Cu crystalgrain boundaries and is hardly diffused into bulk, formed is a structurewherein Ti is contained in large quantity in vicinities 7 a of Cucrystal grain boundaries and Ti is hardly existed in bulk Cu 6 a.

Next, as shown in FIG. 7( h), excessive Ti was removed by hydrofluoricacid, and subsequently by CMP, respective layers of excessive Cu, Ta,and TaN were removed. On this entire front surface, as shown in FIG. 7(i), a SiCN layer (barrier insulating film) 8 a with a thickness of 50 nmwas formed by a plasma CVD method, whereby a first wiring layer wasformed.

Furthermore, as shown in FIG. 7( j), a SiO₂ film (insulating film) 1 c,a SiC film (stopper insulating film) 2 b, a SiO₂ film (insulating film)1 d were formed at thicknesses of 400 nm, 50 nm, and 400 nm,respectively, by a plasma CVD method, and as shown in FIG. 7( k), bylithography and anisotropic dry etching, parts of the SiO₂ film 1 c, SiCfilm 2 b, and SiO₂ film 1 d were removed in order while using the SiCN 8a as an etching stopper, whereby main parts of contact holes (wiringholes) between the first wiring layer and second wiring layer wereformed.

Subsequently, as shown in FIG. 8( l), by lithography and anisotropicetching, while using the SiC film 2 b as an etching stopper, part of theSiO₂ film 1 c was removed, whereby main parts of wiring grooves of thesecond wiring layer were formed. Next, as shown in FIG. 8( m), the SiCNfilm 8 a on bottom portions of the contact holes between the firstwiring layer and second wiring layer and the SiC film 2 b on bottomportions of the second wiring grooves were removed by anisotropicetching, whereby an upper contact surface of the first wiring layer wasexposed.

Next, by slightly etching the front surface by Ar ions in a vacuumsystem, the surface of the first wiring layer exposed from the bottomsof contact holes between the first wiring layer and second wiring layerwas cleaned.

Next, while maintaining a vacuum, in order to coat the inner surfaces ofthe wiring grooves of the second wiring layer and the contact holesbetween the first wiring layer and the second wiring layer, byprocedures similar to those for a first wiring layer formation, as shownin FIG. 8( n), a barrier metal film 3 b provided by laminating a TaNfilm and a Ta film in this order and a 100 nm Cu thin film were formedby an ionization sputtering method, and while using this Cu thin film asa seed, Cu 4 b was buried by an electrolytic plating method.

Next, as shown in FIG. 8( o), simultaneously with a first wiring layerformation, after heat treatment was applied for Cu crystal grain growthin a nitrogen atmosphere, as shown in FIG. 8( p), a Ti film (additionalelement layer) 5 b with a film thickness of 20 nm was formed on theentire Cu front surface by sputtering. Subsequently, as shown in FIG. 8(q), a heat treatment at 350° C. for 30 minutes was performed in anitrogen atmosphere, whereby Ti was diffused into Cu from the Cusurface.

Next, as shown in FIG. 8( r), excessive Ti was removed by hydrofluoricacid, and subsequently by CMP, respective layers of excessive Cu, Ta,and TaN were removed. Thereafter, as shown in FIG. 8( s), on this entirefront surface, a SiCN layer (barrier insulating film) 8 b with athickness of 50 nm was formed by a plasma CVD method, and furthermore, aSiO₂ film 9 was formed as a cover film.

After opening junctions with the second wiring layer in the cover film 9by lithography and etching, Ti film, TiN film, and Al film were formedby sputtering in order, and an Al/TiN/Ti laminated film was processedinto a pad pattern for electrometry by lithography and etching.

COMPARATIVE EXAMPLE

As a comparative example, a conventional semiconductor device having Cuwiring composed of upper-layer and lower-layer wiring was fabricated asshown in the foregoing FIG. 9( a) through (g). The substrate, insulatingfilm, stopper insulating film, barrier metal film, barrier insulatingfilm, and cover insulating film were formed, by use of materials similarto those of the aforementioned embodiment, with similar thicknesses andby a similar forming method. Here, Ti, which was an additional elementin the embodiment, was not added.

(Results of Evaluation)

FIG. 11 shows failure rates of respective samples fabricated by theexample and comparative example. Namely, respective samples of a viachain with a chain number (number of vias) of ten thousand, whosecontact hole diameter was 0.2 μm and whose lower-layer wiring (wiringgrooves) width was 10 μm were fabricated, and failure rates after thesewere stored for 1000 hours at 150° C. were determined.

As a result of a sample processing by Focused Ion Beam (FIB) and anobservation by Transmission Electron Spectroscopy (TEM), it could beconfirmed that disconnections in the respective samples were owed to avoid formation as a result of stress induced migration at thelower-layer wiring portions 4 a of contact holes as reported in theabove-described Japanese Published Unexamined Patent Application No.2001-298084.

In samples of the comparative example, open failures were prominent, andthe failure rate was increased with storage time. In addition, in thesamples of the comparative example, presence of Cu grain boundariescould be confirmed.

On the other hand, in samples of the example, failure has beenremarkably improved. The failure generation rate after the samples werestored at 150° C. for 1000 hours was suppressed to approximatelyone-fortieth of that of the comparative example. Furthermore, byoptimizing the manufacturing processes, failure generation could becompletely suppressed even after storage for 1000 hours.

FIG. 12 shows test results for electromigration resistance of contactholes (contact vias). Concretely, it shows accumulated failureprobabilities with respect to failure time. A test was performed at 300°C. with a condition of a current density of 3.2 MA/cm², a rise inresistivity of 3% was employed as a judgement criterion for failure. Itcould be confirmed that the samples of the example had anelectromigration resistance not less than two times that of the samplesof the comparative example.

It can be considered that, in the example, since diffusion of Cu viagrain boundaries can be suppressed by introducing Ti into Cu crystalgrain boundaries, stress induced migration resistance andelectromigration resistance have been improved.

FIG. 13 shows plotted changes in resistivity. Samples used for thisresistivity measurement are blanket wafer samples which had beenfabricated similarly to the procedures of the above-described embodimentexcept that a Ta/TaN barrier metal film 3 a was formed on a SiO₂insulating film 1 a, a 700 nm Cu layer was further formed, and a 20 nmTi additional element layer 5 a was formed. Here, in the blanket wafersamples, no wiring holes and wiring grooves were formed. In FIG. 13,resistivities at respective manufacturing stages are shown for threesamples of sample 1, sample 2, and sample 3. Herein, sample 1 hasreceived no heat treatment after a Cu film formation before a Ti filmformation, sample 2 has received a heat treatment for Cupolycrystallization at 200° C. for 30 minutes in a nitrogen atmosphereafter a Cu film formation before a Ti film formation and sample 3 hasreceived a heat treatment for Cu polycrystallization at 350° C. for 30minutes.

In comparison with the resistivities after a heat treatment for Cupolycrystallization of Sample 3, for which a heat treatment after a Cufilm formation has been sufficiently performed, a rise in resistivityafter performing a heat treatment to diffuse Ti at 350° C. for 30minutes after a Ti film formation was suppressed to 3% or less in allsamples. As such, a rise in resistivity as a result of a Ti additionfrom the Cu surface is considerably small. This is because Ti which hasbeen added from the surface diffuses along Cu crystal grain boundariesand is hardly introduced in Cu bulk.

FIG. 14 shows results of a measurement, in the aforementioned fabricatedblanket wafer samples, of distributions of Ti, Cu, and N in Cu bysecondary ion mass spectrometry (SIMS). The horizontal axis of the graphin FIG. 14 shows depth of the blanket samples. The vertical axis of thegraph in FIG. 14 shows secondary ion intensity measured by SIMS, whichcorresponds to the quantity of atoms.

Ti with a uniform concentration in a depth direction has been detectedin Cu crystals. Since a Ti diffusion coefficient in bulk Cu is not largein a temperature region on the order of 350° C., it is hardly conceivedthat Ti has diffused in bulk Cu to form a uniform distribution as inFIG. 14, and it is considered that Ti has uniformly diffused up to Cubottom portions via crystal grain boundaries and has thereby been added.Accordingly, it can be considered that Ti has been hardly mixed in bulkCu and has been localized at grain boundaries.

FIG. 15 shows a relationship between resistivities owing to a differencein additional elements and heat treatment. Samples used for thisresistivity measurement are blanket wafer samples which had beenfabricated similarly to the procedures of the above-described embodimentexcept that a Ta/TaN barrier metal film 3 a was formed on a SiO₂insulating film 1 a, a 300 nm Cu layer was further formed, and a Niadditional element layer 5 a was formed. Here, in the blanket wafersamples, no wiring holes and wiring grooves were formed. Here, a filmthickness of the additional element layer was set so that a Niconcentration in Cu becomes 3 atomic % when the additional element Nihas uniformly diffused in Cu. The Ni film was formed by sputtering.

Similarly, respective blanket wafer samples were fabricated byrespectively forming respective films of additional elements of Sn, Cr,and Co in place of the additional element Ni. In FIG. 15, in terms ofrespective blanket wafer samples with additional elements of Ni, Sn, Cr,and Co, shown are resistivities at respective stages after an additionalelement layer formation, after a heat treatment at 350° C. for 30minutes in a nitrogen atmosphere, and after a heat treatment at 400° C.for 30 minutes in a nitrogen atmosphere.

In addition, in FIG. 15, for a comparison, resistivity values of Cuwhere additional element concentration becomes 1 atomic % are shown.Here, these values have been extracted from a publication (authored byC. Kittel, translation supervised by Masao Doyama, “Quantum Theory ofSolids,” MARUZEN Co., Ltd., published 1972, p 338).

As a result, with regard to Sn and Ni, which are easily solid-solved inCu, a rise in resistivity was recognized with the rise in heat treatmenttemperature. Particularly, with regard to Sn, when heat treatment wasapplied at a temperature of 400° C., a rise in resistivity which ishigher than when this was uniformly mixed in Cu at 1 atomic % could berecognized. In contrast thereto, with regard to Cr and Co, whose solidsolubility limits in Cu are low and which form precipitated alloys, arise in resistivity was hardly recognized with the rise in heattreatment temperature. When additional elements which are easilysolid-solved in Cu, such as Cr and Co, are used, resistivity rises evenif these are added from the Cu surface. Accordingly, as the element tobe added from the Cu surface, a precipitating type element whose solidsolubility limit in Cu is low is preferable.

FIG. 16 shows, in terms of a blanket wafer sample which has received aheat treatment at 350° C. for 30 minutes without forming a Ti film onthe Cu surface after a Cu film formation and a blanket wafer sample forwhich Ti film has been formed on the Cu surface after a Cu filmformation and which has received a heat treatment at 350° C. for 30minutes, results of a measurement of oxygen (O) distributions in Cu bySIMS. The horizontal axis of the graph in FIG. 16 shows sample depth. Inaddition, the vertical axis of the graph in FIG. 16 shows secondary ionintensity measured by SIMS. In the sample which has received a heattreatment at 350° C. for 30 minutes without forming a Ti film on the Cusurface after a Cu film formation, an O peak is recognized in thevicinity of an interface between Cu and Ta, whereas in the sample forwhich a Ti film has been formed on the Cu surface after a Cu filmformation and which has received a heat treatment at 350° C. for 30minutes, no O peak is recognized in the vicinity of an interface betweenCu and Ta.

In addition, FIGS. 17( a) and (b) show scanning electron microscope(SEM) photographs of Ta barrier surfaces after, of the samples shown inFIG. 16, for a sample on whose surface a Ti film has been formed, the Taon the surface has been removed by diluted hydrofluoric acid, andfurthermore, for both samples, Cu has been removed by nitric acid. Asshown in FIG. 17( a), in the sample which has received a heat treatmentat 350° C. for 30 minutes without forming a Ti film on the Cu surfaceafter a Cu film formation, a Ta surface at a part where Cu grainboundaries had, presumedly, existed has bulged, and oxidation of Ta atthis part has been confirmed. In contrast thereto, as shown in FIG. 17(b), in a sample for which a Ti film has been formed on the Cu surfaceafter a Cu film formation and which has received a heat treatment at350° C. for 30 minutes, the Ta surface is flat and smooth and no Taoxidation is recognized. These results correspond to the results of anSIMS analysis shown in FIG. 16.

It is considered that the Ta oxidation is due to oxygen on the Cusurface and in Cu which has been diffused by a heat treatment at 350° C.and has oxidized Ta. In the case where a Ti film has been formed on theCu surface, it is considered that the Ti getters oxygen on the Cusurface and in Cu during the following annealing and thereby oxidationof the barrier Ta was suppressed. Accordingly, effects of the Ti film onthe Cu surface includes an effect to suppress barrier Ta from oxidationby gettering oxygen in Cu.

(Modifications of the Invention)

For the wiring metal for a semiconductor device and manufacturing methodtherefor described in the above, the following modifications may beprovided.

In the above-mentioned embodiments, it has been described that thelower-layer wiring and upper-layer wiring could be formed by anidentical method, however, lower-layer wiring and upper-layer wiring maybe formed by different methods by a combination of the above-mentionedrespective embodiments.

As a constituent material of the insulating film 1, SiO₂ and the likeand other insulating materials can be used. As the constituent materialof the insulating film 1, it is preferable to use a materiel of a lowerdielectric constant. The insulating film 1 is formed by a plasma CVDmethod or the like. Although the film thickness of the insulating film 1is not particularly limited, the thickness of the insulating film 1 a ison the order of 100 to 3000 nm, the thickness of the insulating film 1 bis on the order of 100 to 1000 nm, the thickness of the insulating film1 c is on the order of 100 to 1000 nm, and the thickness of theinsulating film 1 d is on the order of 100 to 1000 nm.

As a constituent material of the stopper insulating film 2, insulatingmaterials such as SiC, SiN, SiCN, and the like can be used. As theconstituent material of the stopper insulating film 2, it is preferableto use a material of a lower dielectric constant. The stopper insulatingfilm 2 is formed by a plasma CVD method or the like. Although the filmthickness of the stopper insulating film 2 is not particularly limited,the thickness of the stopper insulating film 2 a is on the order of 10to 100 nm, and the thickness of the stopper insulating film 2 b is onthe order of 10 to 100 nm. In addition, although the stopper insulatingfilm 2 is used as an etching stopper of concavities for wiring, however,if the concavities for wiring can be processed in an objective form, thestopper insulating film 2 is not necessarily used.

The wiring grooves are formed by lithography and etching (anisotropicetching) or the like. Although the width of the wiring grooves is notparticularly limited, normally, these are provided on the order of adiameter of 50 to 20000 nm.

As a constituent material of the barrier metal 3, a substance selectedfrom metals such as Ta, Ti, and W, nitrides of these metals, ternary orquaternary nitrides produced by adding Si or the like to these nitridescan be used. The barrier metal film 3 is formed by an ionizationsputtering method, a CVD method, an Atomic Layer Deposition (ALD) methodor the like. Although the film thickness of the barrier metal film 3 isnot particularly limited, the barrier metal film 3 a is on the order of5 to 50 nm, and the barrier metal film 3 b is on the order of 5 to 50nm.

As a method for forming the metal wiring Cu 4, this can be formed, afterforming a Cu thin film by an ionization sputtering method, a CVD method,a metal-organic chemical vapor deposition method (MO-CVD method) or thelike, by an electrolytic plating method while using this Cu thin film asan electrode or by an MO-CVD method. In addition, it is also possible todirectly bury Cu into wiring grooves by an MO-CVD method without forminga Cu thin film. The film thickness of the metal wiring Cu 4 is notparticularly limited as long as this is formed to such an extent to fillup the wiring grooves and wiring holes.

A heat treatment for Cu crystal grain growth (Cu polycrystallization) isperformed in a reducing atmosphere of nitrogen, hydrogen or the like.This heat treatment is performed at 400° C. or less, and preferably, at300° C. or less. However, this heat treatment step may be omitted.

As a constituent material of the additional element layer 5, Ti, Zr, Hf,Cr, Co, Al, Sn, Mg, Ag and the like can be used. The additional elementlayer 5 is formed by sputtering or the like. Although the film thicknessof the additional element layer 5 is not particularly limited, theadditional element layer 5 a is on the order of 5 to 100 nm, and theadditional element layer 5 b is on the order of 5 to 100 nm.

A heat treatment to diffuse the additional element into Cu 4 from theadditional element layer 5 is performed in an atmosphere of nitrogen orthe like. This heat treatment is performed under a temperature conditionon the order of 300 to 500° C. for 10 minutes to 1 hour.

Removal of an excessive additional element layer 5 is performed by wetetching with hydrofluoric acid or by CMP.

Removal of excessive Cu 4 and an excessive barrier metal film 3 isperformed by CMP.

As a constituent material of the barrier insulating film 8, insulatingmaterials having barrier properties against Cu such as SiCN, SiC, SiNand the like can be used. The barrier insulating film 8 is formed by aplasma CVD method or the like. Although the film thickness of thebarrier insulating film 8 is not particularly limited, the barrierinsulating film 8 a is on the order of 20 to 100 nm, the barrierinsulating film 8 b is on the order of 20 to 100 nm.

Wiring holes are formed by lithography and anisotropic dry etching orthe like. Although the width of the wiring holes is not particularlylimited, normally, these are provided on the order of a diameter of 50to 1000 nm.

As a constituent material of the cover insulating film 9, SiO₂ and thelike and other insulating materials can be used. The cover insulatingfilm 9 is formed by a plasma CVD method or the like. Although the filmthickness of the cover insulating film 9 is not particularly limited,the cover insulating film 9 is on the order of 100 to 10000 nm.

In the above embodiments and example, descriptions have been given whileraising, as an example, a semiconductor device for which metal wiringcomposed of a wiring metal containing polycrystal consisting primarilyof Cu and an additional element other than Cu has been formed on asubstrate on which a semiconductor element has been formed. In thepresent invention, wiring metals having the aforementioned structure andwiring metals manufactured by the aforementioned respectivemanufacturing methods are used as metallic materials for wiring for notonly semiconductor devices but also other uses.

1. A copper alloy for wiring formed by a manufacturing method comprisingthe steps of: forming a polycrystalline Cu film; forming, on thepolycrystalline Cu film, a layer made of an additional element to beadded into the polycrystalline Cu film; diffusing the additional elementfrom the additional element layer into the polycrystalline Cu film viacrystal grain boundaries to form a polycrystalline copper alloy; andsimultaneously therewith performing gettering of oxygen in thepolycrystalline Cu film into the additional element layer, wherein theadditional element is at least one element selected from a groupconsisting of Ti (titanium), Zr (zirconium), Hf (hafnium), Cr(chromium), Co (cobalt), Al (aluminum), Ni (nickel), and Mg (magnesium),and concentration of the additional element is, at grain boundaries ofcrystal grains composing the polycrystalline copper alloy and invicinities of grain boundaries, higher than that of the inside of thecrystal grains, a barrier metal film containing a barrier metal isformed to surround the polycrystalline copper alloy, and concentrationof the additional element is, at the interface between thepolycrystalline copper alloy and the barrier metal film and invicinities of said interface, higher than that of the inside of thecrystal grains, and the barrier metal in the barrier metal film has notbeen oxidized.
 2. A copper alloy for wiring formed by a manufacturingmethod comprising the steps of: forming a polycrystalline Cu film;forming, on the polycrystalline Cu film, a layer made of an additionalelement to be added into the polycrystalline Cu film; diffusing theadditional element from the additional element layer into thepolycrystalline Cu film via crystal grain boundaries to form apolycrystalline copper alloy; and simultaneously therewith performinggettering of oxygen in the polycrystalline Cu film into the additionalelement layer, wherein the additional element is at least one elementselected from a group consisting of Ti (titanium), Zr (zirconium), Hf(hafnium), Cr (chromium), Co (cobalt), Al (aluminum), Sn (tin), Ni(nickel), and Mg (magnesium), and concentration of the additionalelement is, at grain boundaries of crystal grains composing thepolycrystalline copper alloy and in vicinities of grain boundaries,higher than that of the inside of the crystal grains, and an oxide ofthe additional element is formed at said grain boundaries and/or invicinities of said grain boundaries, and a barrier metal in a barriermetal film has not been oxidized.
 3. A copper alloy for wiring formed bya manufacturing method comprising the steps of: forming apolycrystalline Cu film; forming, on the polycrystalline Cu film, alayer made of an additional element to be added into the polycrystallineCu film; diffusing the additional element from the additional elementlayer into the polycrystalline Cu film via crystal grain boundaries toform a polycrystalline copper alloy; and simultaneously therewithperforming gettering of oxygen in the polycrystalline Cu film into theadditional element layer, wherein the additional element is at least oneelement selected from a group consisting of Ti (titanium), Zr(zirconium), Hf (hafnium), Cr (chromium), Co (cobalt), Al (aluminum), Ni(nickel), and Mg (magnesium), and concentration of the additionalelement is, at grain boundaries of crystal grains composing thepolycrystalline copper alloy and in vicinities of grain boundaries,higher than that of the inside of the crystal grains, and concentrationof the additional element in the crystal grains is 0.1 atomic percent orless, and a barrier metal in a barrier metal film has not been oxidized.4. The copper alloy for wiring as set forth in claim 3, wherein at thecrystal grain boundaries and/or in the vicinities of grain boundaries,intermetallic compounds of Cu and at least one element selected from agroup consisting of Ti, Zr, Hf, Cr, Co, Al, Ni, and Mg are formed. 5.The copper alloy for wiring as set forth in claim 3, wherein at thecrystal grain boundaries and/or in the vicinities of grain boundaries,oxides of at least one element selected from a group consisting of Ti,Zr, Fit Cr, Co, Al, Ni, and Mgare formed.
 6. A semiconductor devicecomprising a substrate on which a semiconductor element is formed, and ametal wiring composed of the copper alloy for wiring as set forth in anyone of claims 1, 2, 3, 4 or
 5. 7. The copper alloy for wiring as setforth in any one of claims 2, 3, 4 or 5, wherein concentration of theadditional element at the grain boundaries and in the vicinities ofgrain boundaries is on the order of 2 to 1000 times the additionalelement concentration at the inside of the crystal grains.
 8. The copperalloy for wiring as set forth in claim 3, wherein concentration of theadditional element at the grain boundaries and in the vicinities ofgrain boundaries is on the order of 10 to 100 times the additionalelement concentration at the inside of the crystal grains.